1. Field of the Invention
The present invention relates generally to semiconductor packages and fabrication methods thereof, and more particularly, to a chip scale package (CSP) and a fabrication method thereof.
2. Description of Related Art
A chip scale package is characterized in that the package size is equivalent to the size of the chip that is disposed in the package. U.S. Pat. No. 5,892,179, U.S. Pat. No. 6,103,552, U.S. Pat. No. 6,287,893, U.S. Pat. No. 6,350,668 and U.S. Pat. No. 6,433,427 disclose a conventional CSP structure, wherein a build-up structure is directly formed on a chip without using a chip carrier, such as a substrate or a lead frame, and a redistribution layer (RDL) technique is used to accomplish a redistribution of the electrode pads of the chip to a desired pattern.
However, the application of the RDL technique or disposing of conductive traces on the chip is limited by the size of the chip or the area of the active surface of the chip. Particularly, as chips are developed towards high integration and compact size, they do not have enough surface area for mounting of more solder balls for electrical connection to an external device.
Accordingly, U.S. Pat. No. 6,271,469 provides a fabrication method of a wafer level chip scale package (WLCSP), wherein a build-up layer is formed on the chip of the package so as to provide enough surface area for disposing I/O terminals or solder balls.
Referring to FIG. 1A, an adhesive film 11 is prepared, and a plurality of chips 12, each having an active surface 121 and an opposite inactive surface 122, is provided and attached to the adhesive film 11 via the active surfaces 121 thereof, respectively. Therein, the adhesive film 11 can be such as a heat-sensitive adhesive film. Referring to FIG. 1B, a molding process is performed to form an encapsulant 13 such as an epoxy resin encapsulating the inactive surfaces 122 and side surfaces of the chips 12. Then, the adhesive film 11 is removed by heating so as to expose the active surfaces 121 of the chips 12. Referring to FIG. 1C, by using an RDL technique, a dielectric layer 14 is formed on the active surfaces 121 of the chips 12 and the surface of the encapsulant 13 and a plurality of openings is formed in the dielectric layer 14 to expose the electrode pads 120 of the chips. Then, a wiring layer 15 is formed on the dielectric layer 14 and electrically connected to the electrode pads 120. A solder mask layer 16 with a plurality of openings is further formed on the wiring layer 15, and solder balls 17 are mounted on the wiring layer 15 in the openings of the solder mask layer 16. Subsequently, a singulation process is performed to obtain a plurality of packages.
In the above-described packages, the surface of the encapsulant 13 encapsulating the chip 12 is larger than the active surface 121 of the chip 12 and therefore allows more solder balls 17 to be mounted thereon for electrically connecting to an external device.
However, since the chip 12 is fixed by being attached to the adhesive film 11, deviation of the chip 12 can easily occur due to film-softening and extension caused by heat, especially in the molding process, thus adversely affecting the electrical connection between the electrode pads 120 of the chip 12 and the wiring layer 15 during the subsequent RDL process.
Referring to FIG. 2, since the adhesive film 11 is softened by heat in the molding process, overflow 130 of the encapsulant 13 can easily occur to the active surface 121 of the chip 12 and even contaminate the electrode pads 120 of the chip 12, thus resulting in poor electrical connection between the electrode pads of the chip and subsequently formed wiring layer and even causing product failure.
Referring to FIG. 3A, since the adhesive film 11 supports a plurality of chips 12, warpage 110 can easily occur to the adhesive film 11 and the encapsulant 13, especially when the encapsulant 13 has a small thickness. As such, the thickness of the dielectric layer formed on the chip during the RDL process is not uniform. To overcome this drawback, a hard carrier 18 as shown in FIG. 3B is required so as for the encapsulant 13 to be secured thereto through an adhesive 19, which however complicates the process and increases the fabrication cost. Further, when the RDL process is completed and the hard carrier 18 is removed, some adhesive residue 190 may be left on the encapsulant, as shown in FIG. 3C. Related techniques are disclosed in U.S. Pat. No. 6,498,387, U.S. Pat. No. 6,586,822, U.S. Pat. No. 7,019,406 and U.S. Pat. No. 7,238,602.
In addition, since a WLCSP generally comprises only one chip 12, it has quite limited electrical function. Accordingly, package on package (POP) structures with improved electrical function are proposed. However, such a structure requires plated through holes (PTHs) to achieve interlayer connections, as disclosed by US Patent Application No. 20100072588, No. 20100072606 and No. 20100078655, thus complicating the fabrication process and increasing the fabrication cost.
Therefore, it is imperative to provide a chip scale package and a fabrication method thereof so as to ensure the electrical connection quality between the chip electrode pads and the wiring layer of the package, improve the product reliability, reduce the fabrication cost and allow other semiconductor packages to be stacked without the need of PTHs.